1. Field
Various embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a delayed locked loop (DLL) circuit for generating multi-phase divided clocks.
2. Description of the Related Art
In a semiconductor system (or circuit), a clock is used as a reference signal for adjusting operation timing, and is used to guarantee high-speed operation without errors.
When an externally inputted clock is used within a semiconductor system, clock skew corresponding to the time delay that is caused by an internal circuit of the semiconductor system may occur. When clock skew occurs, a delayed locked loop (DLL) is used to correct the time delay.
As the operating frequency of semiconductor memory devices increases, a multi-phase clock transmission method is employed to transmit the internal clock signal. In the multi-phase clock transmission method, a high-frequency clock is not transmitted as it is, but multiple internal clock signals having lower frequencies are used. For instance, the internal clocks signals having half the frequency of the external clock signal may be generated and transmitted in the semiconductor memory device. Using the multi-phase clock transmission method, the semiconductor memory device may reduce current consumption that is required for transmitting the internal clock, and secure a more stable timing margin for the internal clocks.
As the operating speed of a semiconductor memory device increases, the number of internal clock signals used for the multi-phase clock transmission method is also increased. To generate the internal clock signals, an analog-controlled DLL is generally used.
FIG. 1 is a diagram illustrating a conventional DLL circuit.
Referring to FIG. 1, the DLL circuit includes a dividing unit 110, a delay locked loop (DLL) unit 120, a splitter 130, and a phase correction unit 140.
The dividing unit 110 receives external differential clocks CLK and CLKB, and generates a first internal clock ICK/2 and a second internal clock QCK/2 by dividing the external differential clocks CLK and CLKB, the second internal clock QCK/2 having a phase difference from the first internal clock ICK/2.
The DLL unit 120 includes a delay line unit 121, a replica delay unit 122, a phase comparison unit 123, and a delay control unit 124.
The delay line unit 121 outputs first and second delay locked clocks CK and QCK by delaying the first and second internal clocks ICK/2 and QCK/2 in response to a first delay control signal CTRL1.
The replica delay unit 122 reflects an actual delay of a clock and data path into the first delayed clock CK outputted from the delay line unit 121, and outputs a feedback clock FBCLK. The feedback clock FBCLK is obtained by adding a delay amount of the delay line unit 121 and a delay amount of the replica delay unit 122 to the first internal delay clock ICK/2.
The phase comparison unit 123 compares a phase of the external clock CLK to a phase of the feedback clock FBCLK, and outputs the comparison result UP/DN.
The delay control unit 124 outputs the first delay control signal CTRL1 according to the comparison result of the phase comparison unit 123.
While repeating such a series of operations, the DLL circuit compares the first internal clock ICK/2 to the feedback clock FBCLK. When the two clocks have minimum jitter, they are locked to output the first delay locked clock CK having a desired phase. After locking is achieved an update operation for repeating the locking process is performed at each predetermined period. The update operation is performed to compensate for jitters of the first and second delay locked clocks CK and QCK, which may occur due to noise after locking is achieved.
The splitter 130 may receive the first and second delay locked clocks CK and QCK and generate four-phase clocks ICLK, QCLK, ICLKB, and QCLKB. However, the four-phase clocks ICLK, QCLK, ICLKB, and QCLKB may have phase offsets from each other. The phase offset between the first and second divided clocks ICLK/ICLKB and the third and fourth divided clocks QCLK/QCLKB may occur due to duty distortion of the external differential clocks CLK/CLKB. Furthermore, the phase offset between the first and second divided clocks ICLK and ICLKB and the phase offset between the third and fourth divided clocks QCLK and QCLKB may occur due to duty distortion occurring in the delay line unit 121 and a phase offset occurring in a delay line within the splitter 130. The phase correction unit 140 may remove such offsets and generate final delay locked clocks ICLK_DLL, ICLKB_DLL, QCLK_DLL, and QCLKB_DLL having precise phase relationships relative to each other.
The phase correction unit 140 includes a delay block 141, a driver 142, a multi-phase detection unit 143, and a phase delay control unit 144.
The delay block 141 may include one fixed delay unit 141_1 and three variable delay units 141_2, 141_3 and 141_4. The second divided clock ICLKB, the third divided clock QCLK and the fourth divided clock QCLKB, excluding the first divided clock ICKL, may be delayed through the variable delay units 141_2, 141_3, and 141_4, respectively, and then outputted as clocks having a predetermined phase difference from each other.
The driver 142 may drive the clocks outputted through the delay block 141, and output first and second final delay locked clocks ICLK_DLL/ICLKB_DLL and third and fourth final delay locked clocks QCLK_DLL/QCLKB_DLL. The phases of the first and second final delay locked clocks ICLK_DLL/ICLKB_DLL and the third and fourth final delay locked clocks QCLK_DLL/QCLKB_DLL may be detected through the multi-phase detection unit 143, and a phase error between the respective final delay locked clocks ICLK_DLL, ICLKB_DLL, QCLK_DLL, and QCLKB_DLL may be reduced in response to the second delay control signal CTRL2 outputted through the phase delay control unit 144.
However, each of the variable delay units 141_2, 141_3, and 141_4 included in the delay block 141 inevitably generates a one-bit offset due to the characteristics of digital control. In the conventional DLL circuit shown in FIG. 1, a three-bit offset may be generated as the maximum offset.